1. Field of the Invention
The present invention relates to a method for cleaning cache, and more particularly, to a method for cleaning cache of a specific segment of a processor.
2. Description of the Prior Art
A cache is memory whose access speed is faster than an access speed of general random access memory. Generally, the cache is made of high-speed and expensive static random access memory (SRAM) instead of the slower and cheaper dynamic random access memory (DRAM) used for system main memory. Referring to FIG. 1, because the operating speed of a central processing unit (CPU) 10 is faster than a reading speed of a main memory 12, if the CPU 10 requires to access data stored in the main memory 12, the CPU 10 needs several clock periods to complete the access operation, causing low-efficient implementation. Therefore, when the CPU 10 accesses data, a core 102 first checks whether the required data is in a cache 104. When the required data has been temporally stored in the cache 104 due to the previous operation, the CPU 10 can directly access the required data from the cache 104 instead of accessing the data from the main memory 12. Therefore, the access speed of the CPU 10 can be faster, and the operations of the CPU 10 are more efficient.
Once, the CPU cache was an advanced technique used in supercomputers, but now an instruction cache and a data cache are integrated into a microprocessor used by a computer, and such internal caches are often called L1 caches (Level 1 On-die Cache). In addition, a L2 cache, whose size is greater than L1 cache, was positioned outside the CPU such as a main board or a CPU interface, however, now the L2 cache is a standard component inside the CPU. In addition, the advanced or a workstation CPU may have a L3 cache (Level 3 On-die Cache).
The cache is used to speed up the access speed of the CPU. To fully exert functions of the cache, the cache are not only used to temporally store the data that was accessed before, but also used to move the data, which is to be used in the further, from the main memory with an instruction prediction and a data pre-access technique implemented by hardware. Therefore, the opportunity the CPU can access the required data in the cache can be increased. In addition, because the size/capacity of the cache is limited, how to clean the data stored in the cache is an important topic. In addition, the CPU may provide a write-back command or an invalidate command according to requirements of the system and software. Referring to FIG. 1, when the core 102 performs the write-back operation upon the cache 104, the data stored in the cache 104 is written back to the main memory 12; and when the core 102 performs the invalidate operation upon the cache 104, the core 102 cleans the data stored in the cache 104. Generally, the write-back command is sent with the invalidate command to make the cache be cleaned after the data is written back to the main memory 12. In addition, because the size of the early cache is very small (several kilobytes, KB), there is no need to consider how to clean only a portion of the cache, however, the current cache is expanded to be several megabytes (MB), how to clean a specific segment of the cache becomes a new topic.
In U.S. Pat. No. 6,978,357, Hacking et al. provide a solution to solve this problem. However, Hacking' method has two restrictions; one is that the selected segment must be a multiple of two, and the other one is that the size of the segment to be cleaned is fixed.